Ultra-low power consumption technology
• VDD = single power supply voltage of 1.6 to 5.5 V
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changedfrom high speed (0.03125 μs: @ 32 MHz operationwith high-speed on-chip oscillator) to ultra-low speed(30.5 μs: @ 32.768 kHz operation with subsystemclock)
• Address space: 1 MB
• General-purpose registers: (8-bit register × 8) × 4 banks
• On-chip RAM: 2 to 32 KB
Code flash memory
• Code flash memory: 16 to 512 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (securityfunction)
• On-chip debug function
• Self-programming (with boot swap function/flash shieldwindow function)
Data Flash Memory
• Data flash memory: 4 KB to 8 KB
• Back ground operation (BGO): Instructions can beexecuted from the program memory while rewriting thedata flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 5.5 V
High-speed on-chip oscillator
• Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz,6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
• High accuracy: +/- 1.0 % (VDD = 1.8 to 5.5 V, TA = -20 to +85°C)Operating ambient temperature
• TA = -40 to +85°C (A: Consumer applications, D: Industrial applications )
• TA = -40 to +105°C (G: Industrial applications)
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and reset from 14 levels)
DMA (Direct Memory Access) controller
• 2/4 channels
• Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks
